Neuromorphic computing scaling limits
Bottom line: On chips such as Intel’s Loihi 2, the first hard scaling wall is not raw arithmetic throughput but state/weight density and communication locality: each neuromorphic core has a small local SRAM budget, and spike traffic must be routed over an on-chip/inter-chip event fabric. Verified Answer #1
That is excellent for sparse, event-driven workloads, but it scales poorly when a model starts to look more like a dense transformer, where useful work is dominated by large matrix operations and high fan-in/fan-out connectivity. Verified Answer #1
By contrast, GPU-based transformer systems tolerate dense computation much better because they pair specialized matrix engines with huge HBM pools and high-bandwidth interconnects, but they pay for that with a severe thermal and memory-movement cost. 3D-stacked memristive crossbars could, in theory, remove much of Loihi 2’s SRAM density ceiling by 2028, but they do not automatically solve the full scaling problem: peripheral ADC/DAC overheads, device variability, yield, leakage/sneak paths, and 3D thermal/process-integration limits remain substantial. Verified Answer #1
So my judgment is: plausible for specialized inference-oriented neuromorphic accelerators by 2028; unlikely to eliminate GPUs’ advantage for large dense transformer training by 2028. Verified Answer #1
- What fundamentally limits Loihi 2 scaling? Verified Answer #1
1.1 The limiting resource is local memory, not just “neurons” Intel’s Loihi 2 has 128 neuron cores, each with 192 KB of flexible local memory, for about 24.6 MB total on-chip core memory if you multiply 128 × 192 KB. Verified Answer #1
Intel also lists up to 1 million neurons/chip and 120 million synapses/chip (Intel, 2021/2026). Verified Answer #1
That sounds large, but the important architectural point is that this memory must simultaneously cover: Verified Answer #1
synaptic weights, Verified Answer #1
neuron state, Verified Answer #1
routing/connectivity structures, Verified Answer #1
learning traces / metadata, depending on the model. Verified Answer #1
So the practical ceiling is not just “number of neurons”; it is how much state can be packed into distributed SRAM close to compute. Verified Answer #1
Reproducible calculation Verified Answer #1
128 cores × 192 KB/core = 24,576 KB = 24 MB (binary) ≈ 24.6 MB (decimal). Verified Answer #1
That is tiny relative to a modern AI GPU memory pool. Verified Answer #1
For example, NVIDIA lists 80 GB HBM3 on an H100 SXM, with 3.35 TB/s memory bandwidth and up to 700 W TDP (NVIDIA, 2026). Verified Answer #1
Even just as raw storage, 80 GB / 24.6 MB ≈ 3,250× more memory capacity than Loihi 2’s local neurocore SRAM pool. Verified Answer #1
That comparison is imperfect—HBM and local SRAM serve different roles—but it captures the main point: Loihi 2’s co-located memory is efficient, yet small; GPU memory is farther away and power-hungry, yet vast. Verified Answer #1
1.2 Dense transformer structure is a bad fit for spike-native routing economics Loihi 2’s efficiency comes from event-driven execution and integrated memory+compute, which is ideal when: Verified Answer #1
activity is sparse, Verified Answer #1
only a subset of neurons fire at a given moment, Verified Answer #1
communication is local or compressible, Verified Answer #1
timing matters more than bulk dense FLOPs. Verified Answer #1
Intel’s 2024 Hala Point disclosure makes this dependency explicit: the reported deep-learning efficiency figure was obtained by exploiting up to 10:1 sparsity and 10% activation rates (Intel, 2024). Verified Answer #1
That means the hardware advantage depends heavily on not having dense all-to-all activity. Verified Answer #1
Transformers, however, are dominated by operations that are effectively dense linear algebra: projections, feed-forward layers, and attention-related matrix products. Verified Answer #1
Even if one converts those layers into spiking or graded-spike equivalents, the underlying scaling pressure remains: Verified Answer #1
large parameter matrices must still be represented somewhere, Verified Answer #1
many tokens/features interact across wide dimensions, Verified Answer #1
communication becomes less sparse and less local, Verified Answer #1
event routing traffic rises toward the point where “spikes” behave more like a packetized substitute for dense data movement. Verified Answer #1
So the neuromorphic advantage narrows exactly when model structure becomes more transformer-like. Verified Answer #1
1.3 Communication becomes the second wall after memory Loihi 2 improves multi-chip scaling and router-assisted synchronization, and Intel’s Hala Point system exposes very large aggregate fabric bandwidth numbers. Verified Answer #1
But aggregate bandwidth does not erase the core issue: a spike is a routed message, and scaling manycore SNNs depends on how often those messages must cross core and chip boundaries. Verified Answer #1
The architectural tension is: Verified Answer #1
To keep energy low, you want localized state and sparse events. Verified Answer #1
To represent bigger, denser models, you need more cross-core connectivity. Verified Answer #1
More cross-core connectivity means more routing pressure, more buffering, more synchronization overhead, and more support logic activity. Verified Answer #1
This is why Loihi-like systems often scale best on tasks that are naturally sparse and temporal, rather than dense sequence models that repeatedly touch large weight matrices. Verified Answer #1
1.4 Thermal constraints on Loihi 2 are real, but indirect Loihi 2 is not usually limited by the same single-chip thermal regime as an H100. Verified Answer #1
Intel’s Hala Point system—1,152 Loihi 2 processors, 1.15 billion neurons, 128 billion synapses—has a maximum power of 2,600 W for the full chassis (Intel, 2024). Verified Answer #1
That is far below what a comparable number of GPU-class dense AI accelerators would consume for equivalent dense compute. Verified Answer #1
But that does not mean thermal scaling is irrelevant. Verified Answer #1
It means the bottleneck shifts: Verified Answer #1
Per-chip heat is lower because activity is sparse and arithmetic density is lower. Verified Answer #1
System-level heat reappears when scaling requires many chips, support processors, and interconnects. Verified Answer #1
Hotspots move from dense MAC arrays to routers, SRAM blocks, and support circuitry under heavy communication. Verified Answer #1
Since capacity scales by adding chips, physical packaging/cabling/backplane energy begins to matter sooner than on a giant single-memory-pool GPU design. Verified Answer #1
So the neuromorphic thermal story is: better energy efficiency at useful sparsity, but a capacity-scaling penalty paid in communication fabric and packaging. Verified Answer #1
- Why do GPUs scale dense transformers better, despite awful thermals? Verified Answer #1
2.1 GPUs are built around dense matrix throughput Modern transformer deployment fits GPUs because the dominant workload is regular, high-throughput tensor math. Verified Answer #1
NVIDIA’s H100 SXM specification advertises: Verified Answer #1
80 GB HBM3, Verified Answer #1
3.35 TB/s memory bandwidth, Verified Answer #1
900 GB/s NVLink, and Verified Answer #1
up to 700 W TDP (NVIDIA, 2026). Verified Answer #1
That tells you the design philosophy: large dense models are supported by: Verified Answer #1
huge parameter storage, Verified Answer #1
high-bandwidth movement of activations and weights, Verified Answer #1
specialized tensor cores, Verified Answer #1
scale-out through GPU-GPU links. Verified Answer #1
Architecturally, this is exactly what transformers want. Verified Answer #1
2.2 The GPU’s scaling wall is thermal + memory movement, not representational density The GPU problem is different from Loihi 2’s problem. Verified Answer #1
On GPUs, dense models fit the compute substrate very well. Verified Answer #1
But the cost of repeatedly moving data between HBM/cache/register files and tensor cores is enormous. Verified Answer #1
The result is very high board-level power and cooling demands. Verified Answer #1
In short: Verified Answer #1
Loihi 2 is limited first by state density and communication locality. Verified Answer #1
H100-class GPUs are limited first by energy/thermal cost of dense computation and memory movement. Verified Answer #1
That distinction matters because the question is about scaling limits, not merely energy efficiency on a niche benchmark. Verified Answer #1
- The decisive architectural comparison: Loihi 2 vs GPU transformers Verified Answer #1
Loihi 2 advantage Verified Answer #1
Memory is colocated with compute. Verified Answer #1
Event-driven execution avoids doing useless work on silent neurons. Verified Answer #1
Sparse, temporal, low-latency tasks can be much more efficient. Verified Answer #1
Loihi 2 scaling disadvantage Verified Answer #1
Weight/state capacity is constrained by small distributed SRAM islands. Verified Answer #1
Large fan-in/fan-out graphs stress the routing fabric. Verified Answer #1
Dense transformer-like layers erode sparsity benefits. Verified Answer #1
Capacity expansion requires more chips and more communication fabric. Verified Answer #1
GPU transformer advantage Verified Answer #1
Dense GEMM/attention maps naturally to tensor cores. Verified Answer #1
Large HBM pools tolerate massive parameter counts. Verified Answer #1
Interconnect ecosystems and software stacks are mature. Verified Answer #1
GPU scaling disadvantage Verified Answer #1
Very high TDP. Verified Answer #1
Memory movement dominates energy. Verified Answer #1
Thermal/cooling constraints are severe at cluster scale. Verified Answer #1
So the systems are not merely “better” or “worse”; they are constrained by different first-order scaling laws. Verified Answer #1
- Could 3D-stacked memristive crossbars remove Loihi 2’s density bottleneck by 2028? Verified Answer #1
4.1 Why memristive crossbars are theoretically attractive Memristive crossbars attack precisely the weakest point of Loihi 2-like chips: SRAM area cost per stored weight. Verified Answer #1
A 2025 Nature Communications paper on wafer-scale passive memristive crossbar circuits states that passive crossbars use a 4F² structure and, even assuming ~400% peripheral overhead, could be more than 25× denser than 4-bit SRAM used in neuromorphic inference accelerators; with vertical stacking, density ideally scales as 4F² / n for n stacked layers (Adam et al., 2025). Verified Answer #1
That is the core reason people view 3D memristors as a possible escape hatch from SRAM-bound neuromorphic scaling. Verified Answer #1
Mechanism A 3D-stacked memristive crossbar could help in three ways: Verified Answer #1
Higher synaptic density Verified Answer #1
Synaptic weights are stored as conductance states at crosspoints rather than as SRAM cells and associated logic. Verified Answer #1
In-memory vector-matrix multiplication Verified Answer #1
The same structure that stores weights can perform analog or mixed-signal accumulation, reducing data movement. Verified Answer #1
Vertical scaling Verified Answer #1
Instead of consuming more 2D die area, additional memory/compute layers can be stacked above CMOS logic. Verified Answer #1
If Loihi 2’s main problem is “not enough local weight/state density,” 3D crossbars target exactly that problem. Verified Answer #1
4.2 There is already real evidence that 3D memristive CIM is not purely hypothetical This is not just a thought experiment. Verified Answer #1
A 2022 Nature Electronics paper reported a 3D vertical RRAM computing-in-memory macro fabricated in 55 nm CMOS, explicitly arguing that moving from 2D to 3D can provide higher parallelism, capacity, and density for vector-matrix multiplication. Verified Answer #1
That chip demonstrated an 8-layer 3D VRRAM architecture and reported 58.2 bit/µm² density in the macro (Huo et al., 2022). Verified Answer #1
More recently, a 2024 Nature Communications paper demonstrated a 3-layer stacked memristive crossbar array for reservoir computing, and a 2025 Nature Communications paper pushed toward wafer-scale passive crossbar fabrication while framing these circuits as a path toward “brain-scale neuromorphic computing” (Du et al., 2024; Adam et al., 2025). Verified Answer #1
So by July 19, 2026, the evidence supports this statement: Verified Answer #1
3D memristive crossbars are no longer speculative in principle; what remains uncertain is manufacturable scale, reliability, and system integration. Verified Answer #1
4.3 Why 3D memristive crossbars do not automatically solve everything They solve the density problem more directly than they solve the full-system problem. Verified Answer #1
Peripheral circuits can erase some of the density/energy gains Memristive crossbars need peripheral circuitry for programming, sensing, and data conversion. Verified Answer #1
A 2024 Nature Reviews Electrical Engineering review emphasizes that practical accelerators must balance crossbar density against CMOS peripheral overhead, especially analog-to-digital conversion and programming circuitry (Sebastian et al., 2024). Verified Answer #1
A 2025 Nature mixed-precision memristor/SRAM processor still uses a 5-bit ADC in the memristor-CIM path, illustrating that the crossbar alone is not the whole machine (Khwa et al., 2025). Verified Answer #1
So the true system-level gain is always: Verified Answer #1
crossbar density gain − peripheral overhead − calibration overhead − yield loss. Verified Answer #1
Variability is still a first-class scaling limiter Huo et al. (2022) state directly that scaling to 3D is challenging because of manufacturing and device variability. Verified Answer #1
The 2024 npj review also notes that device-to-device and cycle-to-cycle variation limits the size of models that can be computed reliably without co-optimization across materials, device physics, circuits, and algorithms (Tang et al., 2024). Verified Answer #1
For neuromorphic systems this matters a lot because synapses are the substrate. Verified Answer #1
If synaptic conductances drift, saturate, or vary too much, then added density does not fully translate into usable model capacity. Verified Answer #1
Passive crossbar non-idealities remain serious The 2025 wafer-scale Nature Communications paper lists the classic blockers to practical passive crossbar scaling: Verified Answer #1
leakage / sneak currents, Verified Answer #1
voltage drops, Verified Answer #1
low device yield, Verified Answer #1
speed-retention trade-offs, Verified Answer #1
CMOS-process incompatibilities, Verified Answer #1
labor-intensive calibration, Verified Answer #1
scalability remaining “elusive” in current technology (Adam et al., 2025). Verified Answer #1
These are not cosmetic issues. Verified Answer #1
They directly determine whether a theoretically dense synapse array is usable at system scale. Verified Answer #1
D. 3D thermal/process integration is a genuine constraint A 2024 npj review on monolithic 3D memory-sensing-computing platforms explains a key fabrication constraint: advanced copper/low-κ interconnect stacks are not comfortable above about 400 °C, whereas conventional silicon transistor thermal steps often sit around 600–1000 °C. Verified Answer #1
The same review also notes interconnect self-heating and rising inter-layer parasitic capacitance as layer counts increase (Tang et al., 2024). Verified Answer #1
This matters in two ways: Verified Answer #1
Manufacturing thermal budget: Can you stack the memristive layers without wrecking the underlying CMOS? Verified Answer #1
Operational thermal budget: Can you dissipate heat from tightly stacked active layers plus sensing circuitry without compromising retention, drift, or endurance? Verified Answer #1
So even if 3D stacking improves density, it introduces a new thermal/integration problem that Loihi 2’s 2D SRAM-centric architecture largely avoids. Verified Answer #1
- What could realistically change by 2028? Verified Answer #1
Here I need to be explicit about uncertainty. Verified Answer #1
5.1 What is plausible by 2028 I think the following is plausible to likely by 2028: Verified Answer #1
Specialized 3D memristive neuromorphic inference chips with much higher synapse density than Loihi 2-class SRAM designs. Verified Answer #1
Reason: there is already credible movement from small crossbars to 3D macros to wafer-scale passive fabrication (Huo et al., 2022; Du et al., 2024; Adam et al., 2025). Verified Answer #1
Hybrid architectures rather than “pure memristor brains.” Verified Answer #1
Most likely structure: CMOS logic for control / neuron update / routing + stacked memristive arrays for dense synaptic storage and analog or mixed-signal MAC. Verified Answer #1
Big gains in edge or sparse inference, where model sizes exceed what SRAM-only neuromorphic chips can store locally, but where precision and retraining requirements are modest enough to tolerate analog non-idealities. Verified Answer #1
My confidence on that cluster of outcomes is roughly 60–75%. Verified Answer #1
5.2 What is not likely by 2028 I think the following is possible but unlikely by 2028: Verified Answer #1
Full displacement of GPU-based transformer training by 3D memristive neuromorphic systems. Verified Answer #1
Reason: dense transformer training needs not just storage density, but high precision, stable updates, mature software tooling, and robust interconnect/parallelization strategies. 3D memristive crossbars still face variability and peripheral-overhead constraints, while GPUs already have the ecosystem and manufacturing maturity. Verified Answer #1
A clean one-for-one replacement for Loihi 2 where stacking alone removes all major bottlenecks. Verified Answer #1
Reason: stacking fixes the synapse-density wall much better than it fixes the communication wall, training wall, or precision wall. Verified Answer #1
My confidence that these stronger claims will not be realized by 2028 is roughly 70–80%. Verified Answer #1
- Direct answer to the question Verified Answer #1
Fundamental architectural and thermal constraints limiting SNN scaling on Loihi 2 The key limits are: Verified Answer #1
Distributed SRAM ceiling: Loihi 2’s 128 neurocores each have only 192 KB local memory, so total local state/weight capacity is small compared with GPU HBM pools (Intel, 2021/2026; NVIDIA, 2026). Verified Answer #1
Communication-locality dependence: Loihi 2’s efficiency depends on sparse, event-driven traffic. Verified Answer #1
As workloads become denser and more transformer-like, spike routing overhead rises and the advantage shrinks (Intel, 2024). Verified Answer #1
Poor match to dense transformer algebra: transformers are dominated by dense matrix operations and high fan-in/fan-out interactions, which map naturally to GPUs but stress neuromorphic routing fabrics. Verified Answer #1
System-level thermal scaling through communication fabric: per-chip heat is relatively low, but scaling capacity by adding many chips shifts thermal/power cost into routers, support processors, and interconnects rather than eliminating it. Verified Answer #1
Why GPUs scale dense transformers better GPUs accept the memory-movement penalty and high thermal cost in exchange for: Verified Answer #1
large memory pools, Verified Answer #1
very high memory bandwidth, Verified Answer #1
dense tensor throughput, Verified Answer #1
mature scale-out interconnects. Verified Answer #1
Hence they scale dense transformer architectures better, even though they do so at far higher power. Verified Answer #1
Could 3D-stacked memristive crossbars theoretically overcome density limits by 2028? Yes, in theory, they directly attack the main density limitation of SRAM-based neuromorphic chips. Verified Answer #1
The strongest argument is that passive memristive crossbars can be >25× denser than 4-bit SRAM even with heavy peripheral overhead, and density can ideally improve roughly linearly with the number of stacked layers (4F²/n) (Adam et al., 2025). Verified Answer #1
Existing 3D RRAM computing demonstrations and multi-layer stacked arrays show the concept is technically real, not fictional (Huo et al., 2022; Du et al., 2024). Verified Answer #1
But only partially in practice by 2028. The same literature makes clear that manufacturability, variability, leakage/sneak paths, ADC/programming overhead, yield, and 3D thermal/process integration remain major blockers. Verified Answer #1
So my evaluation is: Verified Answer #1
Likely to overcome local synaptic-density limitations in specialized chips. Verified Answer #1
Unlikely to fully overcome all scaling limitations of neuromorphic SNNs versus GPUs for large dense transformer training by 2028. Verified Answer #1
A precise way to say it is: Verified Answer #1
3D-stacked memristive crossbars could plausibly remove Loihi 2’s first bottleneck (SRAM density), but they probably will not remove the second and third bottlenecks (communication, precision/peripheral overhead, and ecosystem maturity) by 2028. Verified Answer #1
References Verified Answer #1
Adam, G. Verified Answer #1
C., Lee, J., Hassan, K., et al. (2025). Wafer-scale fabrication of memristive passive crossbar circuits for brain-scale neuromorphic computing. Nature Communications, 16, 8757. https://www.nature.com/articles/s41467-025-63831-2 Verified Answer #1
Du, Y., Kim, Y., Moon, J., et al. (2024). 3D-integrated multilayered physical reservoir array for learning and forecasting time-series information. Nature Communications, 15, 2044. https://www.nature.com/articles/s41467-024-46323-7 Verified Answer #1
Huo, Q., Yang, Y., Wang, Y., et al. (2022). A computing-in-memory macro based on three-dimensional resistive random-access memory. Nature Electronics, 5, 469–477. https://www.nature.com/articles/s41928-022-00795-x Verified Answer #1
Intel. (2024, April 17). Intel builds world’s largest neuromorphic system to enable more sustainable AI. Verified Answer #1
Intel Newsroom. https://download.intel.com/newsroom/archive/2025/en-us-2024-04-17-intel-builds-worlds-largest-neuromorphic-system-to-enable-more-sustainable-ai.pdf Verified Answer #1
Intel. (2021/2026). Taking neuromorphic computing to the next level with Loihi 2 [Technology brief]. Verified Answer #1
Intel. https://www.intel.com/content/dam/www/central-libraries/us/en/documents/neuromorphic-computing-loihi-2-brief.pdf Verified Answer #1
Khwa, W.-S., Wen, T.-H., Hsu, H.-H., et al. (2025). A mixed-precision memristor and SRAM compute-in-memory AI processor. Nature, 639, 617–623. https://doi.org/10.1038/s41586-025-08639-2 Verified Answer #1
NVIDIA. (2026). H100 GPU. Verified Answer #1
NVIDIA. https://www.nvidia.com/en-us/data-center/h100/ Verified Answer #1
Sebastian, A., Ielmini, D., Le Gallo, M., et al. (2024). Memristor-based hardware accelerators for artificial intelligence. Nature Reviews Electrical Engineering, 1, 286–299. https://www.nature.com/articles/s44287-024-00037-6 Verified Answer #1
Tang, B., Sivan, M., Leong, J. Verified Answer #1
F., et al. (2024). Solution-processable 2D materials for monolithic 3D memory-sensing-computing platforms: opportunities and challenges. npj 2D Materials and Applications, 8, 74. https://www.nature.com/articles/s41699-024-00508-2 Verified Answer #1