Neuromorphic computing scaling limits

Neuromorphic scaling on hardware like Intel’s Loihi 2 is primarily constrained by state and weight density rather than raw arithmetic throughput Verified Answer #1. Each of the 128 neuron cores on a Loihi 2 chip possesses a limited local SRAM budget of 192 KB Verified Answer #1. This local memory must simultaneously store synaptic weights, neuron states, routing structures, and learning metadata Verified Answer #1. While the architecture supports up to 1 million neurons and 120 million synapses per chip, the total on-chip core memory is approximately 24.6 MB Verified Answer #1.

Communication locality and the event fabric also present scaling challenges Verified Answer #1. These systems excel at sparse, event-driven workloads but face efficiency drops when handling dense models like transformers Verified Answer #1. Dense transformers require large matrix operations and high fan-in/fan-out connectivity, which are better served by the high-bandwidth memory and specialized engines found in GPU-based systems Verified Answer #1.

Future scaling may involve 3D-stacked memristive crossbars to address SRAM density limitations Verified Answer #1. However, this technology introduces new constraints such as peripheral ADC/DAC overhead, device variability, and leakage paths Verified Answer #1. Other persistent hurdles include yield issues and thermal limits associated with 3D process integration Verified Answer #1. While specialized inference accelerators using these technologies are plausible by 2028, they are unlikely to displace GPUs for training large dense transformers within that timeframe Verified Answer #1.