JK flip-flop race-around condition

Overview of the Race-Around Condition

The race-around condition is a state of instability that occurs in level-triggered JK latches when the clock pulse width exceeds the internal propagation delay of the gates Verified Answer #2. In this state, the feedback loop acts as a ring oscillator because the circuit remains transparent while the clock signal is high Verified Answer #2. When the inputs are set to $J=K=1$, the next-state function simplifies to $Q_{next} = \overline{Q}$, causing the output to toggle repeatedly Verified Answer #2.

Mathematical Modeling

In a standard level-triggered latch, the feedback from the outputs to the input steering gates is active continuously during the active-high duration of the clock pulse, denoted as $t_w$ Verified Answer #1. The oscillation frequency of this closed-loop configuration is defined as $f_{osc} = 1/(2\Delta t)$, where $\Delta t$ represents the internal propagation delay Verified Answer #1. The number of toggles that occur during a single clock pulse is calculated by the floor of the ratio between the pulse width and the propagation delay Verified Answer #1.

Predictable operation requires exactly one transition per cycle, implying $t_w < \Delta t$, yet physical gate triggering requires $t_w > \Delta t$ Verified Answer #1. This contradiction results in an indeterminate final state that depends on the specific phase of the oscillation at the moment the clock signal returns to zero Verified Answer #2.

Resolution via Master-Slave Architecture

The Master-Slave (M-S) JK flip-flop resolves the race-around condition by converting the level-sensitive feedback system into a discrete-time, edge-triggered sampling system Verified Answer #2. This architecture introduces a phase-discretization variable that separates the transition function into two distinct phases Verified Answer #2.

• Sampling Phase ($CLK=1$): The Master latch state is updated while the Slave output remains frozen, breaking the feedback loop and creating a stable fixed-point solution Verified Answer #2.
• Transfer Phase ($CLK=0$): The state of the Master is transferred to the Slave while the Master feedback path is disabled Verified Answer #2.

By isolating the state machine phases, the system state only evolves at discrete clock edges Verified Answer #2. This structural change eliminates dependence on the clock pulse width, though it introduces trade-offs regarding silicon area and propagation delay Verified Answer #1.